This invention is directed to semiconductor memory devices, and more particularly, to a semiconductor random access memory cell where the memory cell is a single depletion mode field effect transistor structure.
The earliest semiconductor memories were bipolar, usually transistor-transistor logic (TTL), and were limited in the number of bits per chip. With the development of the metal-oxide-semiconductor (MOS) technologies bit density has increased dramatically. At the present time N-channel MOS memories are being regularly fabricated with 16,384 bits of memory, and devices with 65,536 bits of memory are beginning to reach the market. Even higher density memories are in the design phase. To meet the demands for high density memories new technologies and device designs have been necessary. Originally, most MOS dynamic RAMs used a three-transistor memory cell. This cell is too large for present designs. Today, the one transistor-one capacitor cell is standard. Furture designs will utilize memory cells using only a single MOS transistor. A one-transistor memory cell is used in the array in TAPER ISOLATED RANDOM ACCESS MEMORY ARRAY AND METHOD OF OPERATING by Chatterjee and Taylor, Ser. No. 075574, filed Sept. 14, 1979. A similar structure used as a photodetector is shown in U.S. Pat. No. 4,000,504 by Berger. Both structures suffer from thin gate oxide pinhole problems as the devices are scaled down in size in order to accomodate a larger number of bits on a single chip.